This invention is directed to the field of semiconductor manufacturing and more particularly to a method of reinforcing mechanically compliant dielectrics with mechanical supports.
There are many factors which must be considered when designing the layout for a semiconductor interconnect system. Interconnect systems comprise different components. Two such components are the interlevel dielectrics and the metal line/via structures that are formed. For example, as ever increasing chip speeds are contemplated more complex interlevel dielectrics are being considered. The dielectrics are typically polymers that tend to have the advantage of lower dielectric constants (low k). Some of the low k dielectrics, which also have several advantages for processing purposes, do not have the mechanical integrity of their higher dielectric constant counterparts. By mechanical integrity it is meant that the low k dielectrics are mechanically compliant materials with a small Young""s modulus. The mechanical integrity of the chosen low k dielectric can effect the speed and reliability of the overall semiconductor chip.
There are a number of different ways that a metallization can be formed. Two of the more popular ways are reactive ion etching (RIE) and damascene processing. In RIE, the metallization is first deposited. The metal is then etched and voids created. Possible deposition methods include physical vapor deposition (PVD) and chemical vapor deposition (CVD). The dielectric is then deposited and the voids filled. The dielectric can be deposited by any means known in the art. Possible deposition methods include chemical vapor deposition (CVD), plasma enhanced CVD, high density plasma CVD, or spin-on glass process.
Damascene processes are widely used in the manufacture of semiconductor devices. Generally, in a damascene process, a dielectric layer is first deposited on a substrate, a portion of the dielectric layer is then removed by an etching process in accordance with a mask pattern, the etched areas in the dielectric layer are lined with a barrier metal and then filled with a metal, and finally the excess liner and metal deposited over the dielectric layer are removed in a planarization process. By this method, metal features such as vias or lines are formed on a substrate.
Vias and lines can be formed in separate damascene processes, known as single damascene. For example, to form a layer of metal lines on a substrate, a dielectric layer is first deposited, then a portion of the dielectric layer is etched according to a mask pattern which corresponds to the desired line pattern, a metal liner is then deposited on the dielectric layer and in the etched line areas in the dielectric layer, these etched line areas are then filled with a metal, and finally the excess metal and liner on top of the dielectric layer is removed in a planarization process. A layer of vias is formed in a similar process, except that the mask pattern corresponds to the desired via pattern. Thus, to form a layer of vias and lines, two metal fill steps and two metal planarization steps are required.
In the electronics industry, there is a current trend toward using more cost effective dual damascene in the fabrication of interconnection structures. In a dual damascene process, both the via and the line are formed in the same damascene process. In one way to form the via and the line in the same damascene process, a thicker dielectric layer is first deposited on a substrate, the dielectric layer is then etched according to a mask pattern which corresponds to both the desired via pattern and the desired line pattern, a liner is then deposited on the dielectric layer and in the etched areas in the dielectric layer, these etched areas are then filled with a metal, and the excess metal and liner is removed by a planarization process. This dual damascene process therefore reduces the number of costly metal fill and planarization steps. It should be realized that in some dual damascene processes the via and line patterns can be defined in separate lithography and etch steps.
However, it is well known that interconnection structures are susceptible to failure caused by electromigration effects. For example, FIG. 1 illustrates a cross sectional view of a wafer stack 100 formed using a conventional dual damascene process. The wafer stack 100 includes a substrate 102, an oxide layer 104, a metal layer 106, a dielectric layer 108, a liner 110, a metal via 112 and a metal line 114. The metal via 112 and metal line 114 are formed by a dual damascene process in which the dielectric layer 108 is first deposited on top of the metal layer 106, the dielectric layer 108 is then etched to form via 112 and trench 114 according to a mask pattern which defines the desired via and line pattern, the liner 110 is deposited on the dielectric layer 108 and in the etched portions of the dielectric layer 108, a metal is then deposited in the via 112 and trench 114, and finally the excess metal and liner on top of the dielectric layer 108 are removed by a planarization process.
In this wafer stack configuration, when an electric potential is applied across the metal via 112 and metal line 114, the electric potential causes an electromigration effect in the metal via 112 and metal line 114. Specifically, the electric potential causes one portion of the interconnect structure to be a cathode and the other portion to be an anode. While there is no demarcation in a metal line for the end of the cathode end and the beginning of the anode end, for the purposes of this invention the anode end of the line shall be equal to at most 50% of the line length. The electric potential between the cathode and the anode causes a current flow from the anode end to the cathode end through metal via 112 and metal line 114. Since the direction of electrons is opposite of the direction of current flow, the electron current is from the cathode end of the metal via 112 toward the anode end of the metal line 114. In this process, the moving electrons generate an xe2x80x9celectron windxe2x80x9d which pushes or forces the metal atoms in the direction of the electrons from the metal via 112 near the cathode to the metal line 114 near the anode. The liner 110 prevents the atoms in the metal layer 106 from migrating to the metal via 112 and metal line 114. As a result, a void 116 forms near the cathode in the metal via 112. The formation of this void often leads to catastrophic failure of the device. The failure is catastrophic because the liner 110 at the bottom of the via 112 is often thinner than in the line and therefore is unable to shunt the current across the void.
Also, metal atoms tend to pile up near the anode end of the interconnects during electromigration. The accumulation of metal atoms creates mechanical compressive stress which has the potential of creating cracks in the surrounding dielectric materials. As a result, the electromigrated metal atoms tend to extrude out through the cracks in the dielectric. The extruded material may then contact neighboring interconnects causing circuit failure (short circuit).
Void (and extrusion) formation due to electromigration is a well known phenomenon. Several methods have been proposed to counteract this electromigration effect in interconnects and thereby prevent void formation. For example, in IBM Technical Disclosure Bulletin Vol. 31, No. 6 (1988), tungsten (W) links are interposed periodically in long aluminum-copper (Alxe2x80x94Cu) lines or minimum groundrule features interfacing contact pads. These tungsten links form a physical barrier to the Alxe2x80x94Cu atoms being transported between the cathode to the anode. As another example, U.S. Pat. No. 5,470,788 to Biery et al. proposes interposing segments of Al with segments of refractory metal such as W.
Each of these methods is based on the existence of an electromigration threshold condition. Threshold conditions occur in adjacent levels of interconnections if an electrical current is supplied through leads of materials in which a diffusion barrier exists. The physical origin of the electromigration threshold is the build-up of backstress. As interconnection metal atoms pile up against the diffusion barrier leads, this backstress counteracts the electromigration driving force. A steady-state condition arises in situations where the backstress exactly balances the electromigration driving force. Under this condition, no further electromigration damage occurs.
The equation for the net electromigration flux (Jem) which is valid for metal lines for any length within a given dielectric, is given by the following equation:
Jem=D/kT[Z*ejxcfx81xe2x88x92(xcex4"sgr"/xcex4x)xcfx89] where: 
D=diffusivity of metal
k=Boltzmann""s constant
T=temperature
Z*=effective ion charge
e=electron charge
j=current density
xcfx81=resistivity of metal
(xcex4"sgr"/xcex4x)=mechanical stress gradient over interconnect
xcfx89=atomic volume of metal
Z*ejxcfx81 represents the electron wind force discussed above. The (xcex4"sgr"/xcex4x)xcfx89 term represents the stress driven backflow discussed above. While the electron wind force value is independent of line length, the stress driven backflow term is dependent on dielectric mechanical strength and line length. For example, as the mechanical strength of the dielectric decreases the stress driven backflow decreases. Also, as the line length increases, the stress driven backflow decreases. Therefore, it can be seen that one method of reducing the Jem when premature electromigration failure is a concern would be to increase the stress driven backflow. Thus, there remains a need for a structure that balances the need for increasing the stress driven backflow and/or mechanical strength of the dielectric when using low k materials and/or long metal lines.
It is therefore an object of the present invention to provide a structure to mechanically reinforce the anode portion of a metallization/dielectric system.
It is a further object of the present invention to provide a structure that increases the stress driven backflow in a low dielectric constant material.
In accordance with the above listed and other objects, we claim a reinforced semiconductor interconnect structure, comprising:
A first metal interconnect disposed in a first material, the first metal interconnect having a line portion and at least one via portion, an anode section and a cathode section, the via portion of the first metal interconnect located in the anode section, the line portion of the first metal interconnect having a top, bottom and terminus side, wherein at least a part of the bottom side of the line portion of the first metal interconnect in contact with the first dielectric;
a first reinforcement disposed in the first material, the first reinforcement in contact with at least the bottom side of the first metal interconnect, the first reinforcement comprising a second material, the second material being electrically nonconductive; and wherein the second material has a greater mechanical rigidity than the first material.